Communication channels are employed in communication systems. Communication channels transmit multi-bit data between, for example, a line card and a switching fabric. FIG. 1 illustrates relevant components (shown in block diagram form) of an exemplary communication channel 10. Communication channel 10 and the written description thereof should not be considered prior art to the invention described and/or claimed herein.
Communication channel 10 includes communication paths 12–16 coupled between an input node 18 and an output node 20. Communication paths 12–16 include transmitter circuits 22–26, respectively, coupled to receiver circuits 32–36, respectively, via serial communication links 42–46, respectively.
A stream of N-bit input data is provided to input node 18. Each N-bit input data is divided into three N/3-bit data portions. The N/3-bit data portions are synchronously provided to respective inputs of transmitters 22–26. Transmitters 22–26 transmit their respective N/3-bit data portion to receivers 32–36, respectively, in a bit-by-bit fashion over serial links 42–46, respectively. Receivers 32–36 output respective N/3 data portions in parallel format. The N/3-bit data portions from receivers 32–26 are concatenated to form N-bit output data at output node 20.
A time delay exists in the transmission of the N/3-bit data portions through each of the communication paths 12–16. If communication paths 12–16 were identical in structure and if communication paths 12–16 operated under identical conditions, the transmission delays through communication paths 12–16 would be identical. Unfortunately, communication paths 12–16 vary in physical structure and operating conditions. For example, serial links 42–46 may consist of traces on a printed circuit board. The traces may vary in length. Further, each of the transmitter circuits 22–26 is provided with a power supply. Unfortunately, the magnitude of the power supply voltage may vary between transmitter circuits 22–26. Receiver circuits 32–36 may operate at different temperatures. Transmitter circuits 22–26 and receiver circuits 32–36 operate in accordance with a clock signal provided thereto. Unfortunately, the distribution of the clock signal between, for example, transmitter circuits 22–26 may be uneven such that the rising and falling edges of the clocks to transmitter circuits 22–26 may be skewed with respect to each other. Transmitters 22–26 may be formed on the same integrated circuit, and the conductive paths that transmit the clock signal to transmitter circuits 22–26 may be uneven in length from the source of the clock signal. The difference in conductor lengths may cause skew between clock signals provided to transmitter circuits 22–26. Each link 42–46 may operate according to a unique clock domain. Clock domain crossing is another source of variation between links 42–46. Lastly, transmitters 22 and 26 should be identical in physical structure to each other. Unfortunately, variations in the process to manufacture components (e.g., transistors) within transmitters 22–26, may result in physical differences between transmitters 22–26.
The aforementioned physical structure and/or operating condition variations may result in relative transmission delays between communication paths 12–16. For purposes of explanation, it will be presumed that the transmission delays of communication paths 14 and 16 are greater than the transmission delay of communication path 12, and that the transmission delay of communication path 16 is greater than the transmission delay of communication path 14 due to physical structure and/or operating condition variations. To illustrate the effect of these relative transmission delays between communication channels 12–16, suppose an N-bit input data value A is provided to input node 18 at time t1. A is divided into N/3-bit data portions A1, A2, and A3. A1, A2, and A3 are synchronously input into communication paths 12–16, respectively. Because of the presumed relative time delays between communication paths 12–16, A2 outputs from communication path 14 one clock cycle after A1 outputs from communication path 12, and A3 outputs from communication path 16 two clock cycles after A1 outputs from communication path 12. Thus, A1–A3 emerge from communication paths 12–16, respectively, out of synchronization. Because A1–A3 are out of synchronization, A1–A3 cannot be concatenated in communication path 10 to reproduce A at output node 20.